The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, and particularly relates to a technique effectively applied to a semiconductor integrated circuit device having a wiring pattern formed by a lithography technique adopting a phase shift and to a manufacturing technique therefor.
A lithography technique adopting a Levenson type phase shift capable of improving resolution by ensuring a fixed focal depth has been studied as one of methods of forming a fine wiring pattern.
There have been proposed several methods of arranging phase shifters for a phase shift mask. For example, Japanese Patent Laid-open No. 7-234500 by Ohi et al. discloses a method of executing compaction, in which patterns have the same phase, other patterns between and adjacent to the patterns are given as opposite a phase as possible, and the condition is added that the shortest distance S1 between the other patterns having the opposite phase is below the shortest distance S2 between the patterns having the same phase (S1 less than S2).
Further, Japanese Patent Laid-open No. 9-152709 by Sawada discloses a method of selecting sequentially phase-undefined patterns, determining phases of the selected patterns in accordance with adjacent pattern phase information thereof so as to be different from phases which most patterns adjacent to the selected patterns have, and updating contents of data of the determined phases.
In addition, Japanese Patent Laid-open No. 6-85202 by Tanaka et al. discloses a method of designing placement of phase shifters in a direction of each shorter dimension of patterns so that relationships between phases of light beams emitted from both openings and other openings adjacent thereto are always opposite to each other.
Also, Japanese Patent Laid-open No. 5-304211 by Itoh discloses a method of connecting a set of boundary wiring formed by making amounts of phase shift changed gradually, to one set of wiring formed by a phase shift method and the other set of wiring formed by no phase shift method.
Further, Japanese Patent Laid-open No. 7-13326 by Ohi et al. discloses a method of obtaining an adjacency relationship depending on whether the shortest length between figures corresponding to transparent regions in mask layout data is below a certain threshold value, giving a weight to each of portions becoming closed loops constituting odd nodes in accordance with the adjacency relationship, and thereby determining the phase of light with respect to the respective transparent regions.
Moreover, Japanese Patent Laid-open No. 6-35171 by Takekuma discloses a method of separating pattern data into an actual pattern data layer and a phase shift pattern data layer, and then verifying a mask pattern.
Although it is possible to narrow wiring placement intervals by using the above-mentioned Levenson type phase shift, there occurs the problem that parasitic capacity (coupling capacity) between sets of wiring increases and thereby delay time of each set of wiring increases.
Further, when a phase shift mask is manufactured, because a designer must redesign each shape, dimension, and position of phase shifters and must manually rearrange the phase shifters relative to contradictory portions which cannot invert a phase, a step of designing a mask pattern requires longer time.
An object of the present invention is to provide a technique capable of preventing the parasitic capacity between the sets of wiring from increasing, and capable of narrowing the wiring placement intervals.
Another object of the present invention is to provide a technique capable of efficiently carrying out phase shift mask design operation.
These and other objects of the present invention as well as novel features of the present invention will be readily apparent from the description of the present specification and accompanying drawings.
Among the inventions disclosed in the present application, typical inventions will be outlined briefly as follows.
(1) According to the semiconductor integrated circuit device of the present invention, a set of wiring transferred by Levenson type phase shift exposure and included in an automatic routing region is constituted by a first wiring group having a first width and a second wiring group having a second width; and said first width is relatively larger than said second width.
(2) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (1), an interval between a set of first wiring and a set of second wiring is narrower than a minimum wiring interval provided without using Levenson type phase shift, the set of second of wiring being put between the adjacent sets of first wiring.
(3) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (2), said first wiring is longer than said second wiring.
(4) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (3), plural sets of second wiring are placed between a pair of sets of first wiring adjacent to each other.
(5) According to the semiconductor integrated circuit device of the present invention, a set of signal wiring placed in a wiring region formed in a semiconductor chip is divided into a set of long wiring and a set of short wiring by comparison with a reference value; and said set of long wiring is arranged in parallel to said set of short wiring and in proximity to at least one side of said set of short wiring.
(6) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (5), an interval between said set of long wiring and said set of short wiring provided in parallel and in proximity thereto is narrow relatively narrower than an interval between sets of long wiring provided in parallel to each other.
(7) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (5), a width of said set of short wiring is 0.3 to 1.0 times as large as a width of said set of long wiring.
(8) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (6), a width of said set of short wiring is 0.3 to 1.0 times as large as a width of said set of long wiring.
(9) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (5), wiring layer constituting a set of signal wiring extending in lateral direction differs from a wiring layer constituting a set of signal wiring extending in longitudinal direction; and the wiring layer extending in the lateral direction and the wiring layer extending in the longitudinal direction, which constitute one-net, are connected to each other through a contact hole provided in an interlayer insulating film between said wiring layer extending in the lateral direction and said wiring layer extending in the longitudinal direction.
(10) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (5), said reference value is K times as high as an average value of spreads of a net in the wiring region, M times as large as a width of an interior of the wiring region, N% of the spread of the net on a shorter side in a wiring length distribution, one of an allowable length of the set of short wiring in view of resistance characteristics determined by a current density of the set of wiring and an allowable length of the set of long wiring in view of capacitive characteristics, and a combination thereof.
(11) The manufacturing method of the semiconductor integrated circuit device of the present invention, comprises the steps of: having a first wiring group with a first width and a second wiring group with a second width; and transferring a wiring pattern in an automatic routing region by Levenson type phase shift exposure, the wiring pattern in which said first width is relatively larger than said second width.
(12) According to the manufacturing method of the semiconductor integrated circuit device of the present invention based on above-mentioned (11), an interval between a set of first wiring and a set of second wiring is narrower than a minimum wiring interval provided without using Levenson type phase shift, the set of second wiring being put between the adjacent sets of first wiring.
(13) According to the manufacturing method of the semiconductor integrated circuit device of the present invention based on above-mentioned (12), said first wiring is longer than said second wiring.
(14) According to the manufacturing method of the semiconductor integrated circuit device of the present invention based on above-mentioned (13), plural sets of second wiring are placed between a pair of sets of first wiring adjacent to each other.
(15) The manufacturing method of the semiconductor integrated circuit device of the present invention, comprises the steps of: dividing a set of signal wiring into a set of long wiring and a set of short wiring by comparison with a reference value; arranging said set of long wiring in parallel to said set of short wiring and in proximity to at least one side of said set of short wiring; and forming a set of signal wiring in a wiring region included in a semiconductor chip.
(16) The manufacturing method of the semiconductor integrated circuit device of the present invent jased on above-mentioned (15), further comprises the steps of: making a layout rule of said set of long wiring different from a layout rule of said set of short wiring; and making an interval between a set of long wiring and a set of short wiring provided in parallel and in proximity thereto relatively narrower than an interval between sets of long wiring arranged in parallel to each other, by using a Levenson type phase shifter to expose a pattern of said set of short wiring on a photomask.
(17) The manufacturing method of the semiconductor integrated circuit device of the present invention based on above-mentioned (15), further comprises the steps of: making a layout rule of said set of long wiring different from a layout rule of said set of short wiring; and making a width of said set of short wiring 0.3 to 1.0 times as large as a width of said set of long wiring, by using a Levenson type phase shifter to expose a pattern of said set of short wiring on a photomask.
(18) The manufacturing method of the semiconductor integrated circuit device of the present invention based on above-mentioned(16), further comprises the steps of: making a layout rule of said set of long wiring different from a layout rule of said set of short wiring; and making a width of said set of short wiring 0.3 to 1.0 times as large as a width of said set of long wiring, by using a Levenson type phase shifter to expose a pattern of said set of short wiring on a photomask.
(19) The manufacturing method of the semiconductor integrated circuit device of the present invention based on above-mentioned (15), further comprises the steps of: making a wiring layer constituting a set of signal wiring extending in lateral direction different from a wiring layer constituting a set of signal wiring extending in longitudinal direction; and connecting the wiring layer extending in the lateral direction and the wiring layer extending in the longitudinal direction, which constitute one net, through a contact hole provided in an interlayer insulating film between said wiring layer extending in the lateral direction and said wiring layer extending in the longitudinal direction.
(20) According to the manufacturing method of the semiconductor integrated circuit device of the present invention based on above-mentioned. (15), said reference value is K times as high as an average value of spreads of a net in the wiring region, M times as large as a width of an interior of the wiring region, N% of the spread of the net on a shorter side in a wiring length distribution, one of an allowable length of the set of short wiring in view of resistance characteristics determined by a current density of the set of wiring and an allowable length of the set of long wiring in view of capacitive characteristics, and a combination thereof.
The other features of the present invention will be described according to items as follows:
1. A photomask design method for manufacturing the semiconductor integrated circuit device of the present invention has the step of:
(a) dividing a wiring region included in a semiconductor chip into rectangular regions;
(b) dividing a set of signal wiring into a set o long wiring and a set of short wiring in longitudinal and lateral directions, respectively, by comparison with a reference value;
(c) allocating the set of long wiring to wiring region so that said set of long wiring is averagely present without detoruing;
(d) alternately allocating wiring tracks of 0xc2x0 in pahse and wiring tracks of 180xc2x0 in phase in the longitudinal and lateral directions to said region, respectively;
(e) allocating said set of long wiring to wiring tracks 0xc2x0 in phase, and said set of short wiring tracks of 180xc2x0 in phase; and
(f) making a layout rule of said set of long wiring different from a layout rule of said set of short wiring in layout design, and determining coordinates of said set of long wiring and said set of short wiring by using an effect of Levenson type phase shift.
2. A photomask desing method for manufacturing the semiconductor integrated circuit device of the present invention has the step of:
(a) dividing a wiring region included in a semiconductor chip into rectangular regions;
(b) dividing a set of signal wiring into a set of long wiring and a set of short wiring in longitudinal and lateral directions, respectively, by comparison with a reference value;
(c) allocating said set of long wiring to a wiring region so that said set of long wiring is averagely present without detouring;
(d) alternately allocating wiring tracks 0xc2x0 in phase and wiring tracks of 180xc2x0 in phase in the longitudinal and lateral directions to said wiring region, respectively;
(e) allocating said set of long wiring to the wiring tracks 0xc2x0 in phase, and the set of short wiring to wiring tracks 180xc2x0 in phase;
(f) correcting allotment of said set of long wiring; and
(g) making a layout rule of said set of long wiring different from a layout rule of the set of short wiring in layout desing, and determining coordinates of the set of long wiring and the set of short wiring by using an effect of a Levenson type phase shift.
3. A photomask desing method for manufacturing the semiconductor integrated circuit device of the present invention has the steps of:
(a) dividing a wiring region included in a semiconductor chip into regular regions;
(b) dividing a set of signal wiring into a set of long wiring and a set of short wiring in longitudinal and lateral directions, respectively, by comparison to a reference valure;
(c) allocating the set of long wiring to a wiring region so that said set of long wiring is averagely present without detouring;
(d) altenately allocating wiring tracks of 0xc2x0 in phase and wiring tracks of 180xc2x0 in phase in the longitudinal and lateral directions to said wiring region, respectively;
(e) allocating said set of long wiring to said wiring tracks 0xc2x0 in phase, and said set of short wiring to said tracks 180xc2x0 in phase;
(f) making a layout rule of said set of long wiring different from a layout rule of said set of short wiring in layout design, placing the set of long wiring and the set of short wiring so as to make an interval between a set of long wiring and a set of short wiring provided in parallel and in proximity to each other relatively narrower than an interval between sets of long wiring provided in parallel to each other by using an effect of a Levenson phase shift, and determining coordinates thereof.
4. According to a photomask design method for manufacturing the semiconductor integrated circuit device of the present invention based on the photomask design method recited in above-mentioned item 1, a width of said sdet of short wiring is 0.3 to 1.0 times as large as a width of said set of long wiring.
5. According to a photomask design method for manufacturing the semiconductor integrated circuit device of the present invention based on the photomask design method recited in above-mentioned item 2, a width of said set of short wiring is 0.3 to 1.0 times as large as a width of said set of long wiring.
6. According to a photomask design method for manufacturing the semiconductor integrated cirucit device of the present invention based on the photomask design method recited in above-mentioned item 3, a width of said set of short wiring is 0.3 to 1.0 times as large as a width of said set of long wiring.
7. According to a photomask design method for manufacturing the semiconductor integrated circuit device of the present invention based on the photomask design method recited in above-mentioned item 1, the set of long wiring placed on the wiring track of 0xc2x0 in phase is designed according to a layout rule not using a phase shifter, and the set of short wiring placed on the wiring tracks of 180xc2x0 in phase are designed according to a layout rule using the phase shifter.
8. According to a photomasd design method for manufacturing the semiconductor integrated circuit device of the present invention based on the photomask design method recited in above-mentioned item 2, the set of long wiring placed on the wiring track of 0xc2x0 in phase are designed according to a layout rule not using a phase shifter, and the set of short wiring placed on the wiring track of 180xc2x0 in phase are designed according to a layout rule using the phase shifter.
9. According to a photomask design method for manufacturing the semiconductor integrated circuit device of the present invention based on the photomask design method recited in above-mentioned item 3, the set of long wiring placed on the wiring track of 0xc2x0 in phase is designed according to a layout rule not using a phase shifter, and the set of short wiring placed on the wiring track of 180xc2x0 in phase is designed according to a layout rule using the phase shifter.
10. According to a method of designeing a photomask for manufacturing the semiconductor integrated circuit device of the present invention based on the photomask design method recited in above-mentioned item 1, one of an interval between the sets of long wiring and an interval between the sets of short wiring allotted to the same wiring track so as to be adjacent to each other is set to be equal to or larger than a minimum processed dimension which can be processed without using the Levenson type phase shift.
11. According to a method of designing a photomask for manufacturing the semiconductor integrated circuit device of the present invention based on the photomask design method recited in above-mentioned item 2, one of an interval between the sets of long wiring and an interval between the sets of short wiring allotted to the same wiring track so as to be adjacent to each other is set to be equal to or larger than a minimum processed dimension which can be processed without using the Levenson type phase shift.
12. According to a method of designing a photomask for manufacturing the semiconductor integrated circuit device of the present invention based on the photomask design method recited in above-mentioned item 3, one of an interval betrween the sets of long wiring and an interval between the sets of short wiring alotted to the same wiring track to be adjacent to each other is set to be equal to or wider than a minimum processed dimension which can be processed without using the Levenson type phase shift.
13. According to a photomask design method for manufacturing the semiconductor integrated circuit devie of the present invention based on the photomask design method recited in above-mentioned item 1, a wiring layer consituting a set of signal wiring extending in lateral direction is made different from a wiring layer consistuting a set of signal wiring extending in longitudinal direction, and the wiring layer extending in the lateral direction and the wiring layer extending in the longitudinal direction, which consitute one net, are connected through a contact hole provided in an interlayer Insulating film between said wiring layer extending in the lateral direction and said wiring layer extending in the longitudinal direction.
14. According to a photomask dsign method for manufacuting the semiconductor integrated circuit device of the present invention based on the photomask design method recited in above-mentioned item 2, a wiring layer consituting a set of signa wiring extending in lateral direction is made different from a wiring layer constituing a set of signal wiring extending in longitudinal direction, and the wiring layer extending in the lateral direction and the wiring layer extending in the longitudinal directino, which consitute one net, are connected through a contact hole provided in an interlayer insulating film between said wiring layer extending in the lateral direction and said wiring layer extending in the longitudinal direction.
15. According to a photomask design method for manufacturing the semiconductor integrated circuit device of the present invention based on the photomask design method recited in above-mentioned item 3, a wiring layer constituting a set of signal wiring extending in lateral direction is made different from a wiring layer constituing a set of signal wiring extending in longitudinal direction, and the wiring layer extending in the lateral directin and the wiring layer extending in the longtiudinal direction, which constitute on net, are connected through a contact h ole provided in an interlayer insulating film between said wiring layer extending in the lateral directin and said wiring layer extending in the longitudinal direction.
16. According to a photomask design method for manufacturing the semiconductor integrated circuit device of the present invention based on the photomask design method recited in above-mentioned item 1, said reference value is K times as high as an average value of the spread of nets in the wiring region, M times as large as a width of an interior of the wiring region, N% of the spread of the nets on a shorter side in a wiring length distribution, one of an allowable length of the set of short wiring in view of resistance characteristics determined by a current density of the sets of wiring and an allowable length of the set of long wiring in view of capacitive sharacteristics, and a combination thereof.
17. According to a photomask design method for manufacturing the semiconductor integrated circuit device of the present invention based on the photomask design method recited in above-mentioned item 2, said reference value is K times as high as an average value of the spread of nets in the wiring region, M times as large as a width of an interior of the wiring region, N% of the spread of the nets on a shorter side in a wiring length distribution, one of an allowable lenth of the set of short wiring in view of resistance charateristics determined by a curren density of the set of wiring and an allowable length of the sets of long wiring in view of capacitive characteristics, and a combination thereo.
18. According to a photomask design method for manufacturing the semiconductor integrated circuit device of the present invention based on the photomask design method recited in above-mentioned item 3, said reference value is K times as high as an average value of the spread of nets in the wiring region, M times as large as a width of an interior of the wiring region, N% of the spread of the nets on a shorter side in a wiring length distribution, one of an allowable length of the set of short wiring in view of resistance characteristics determined by a current density of the set of wiring and an allowable length of the set of long wiring in view of capacitive characteristics, and a combination thereof.
According to the above-mentioned present invention, the interval between a set of short wiring and a set of long wiring is determined in accordance with the layout rules using the Lev nson type phase shift. It is, therefore, possible to make the interval relatively narrower than an interval determined in accordance with the layout rules not using the Levenson type phase shift, and to reduce the area of the wiring region. Also, the number of sets of long wiring provided in parallel to each other is decreased, and the interval between the sets of long wiring is determined in accordance with the layout rules not using the Levenson type phase shift, and the set of short wiring are put between the sets of long wiring in many cases. Therefore, it is possible to prevent the sets of long wiring from being provided in parallel and in proximity to each other, and to suppress an increase in the parasitic capacity of the sets of long wiring to prevent an increase in delay time. Furthermore, at the time of manufacturing a phase shift mask, wiring tracks different in phase are alternately arranged in advance so as to invert each phase of adjacent patterns, and the sets of short wiring and the sets of long wiring are alternately allotted to the above-mentioned wiring tracks. Due to this, no contradictory portion occurs and no number of steps of correcting layout thereof occurs.